Application Engineer

CadenceDesignSystems (Belo Horizonte MG, Brasil) Publicado 2 dias atrás

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems is looking for a candidate to be part of its Verification team as an Application Engineer with focus on Jasper formal tool. If you like to architect and develop solutions for challenging problems in a fast and innovative paced environment, using state of the art technology this is a great opportunity.

This position is located in Belo Horizonte.

Job Description:
As an integral member of the Field Applications Engineering (AE) Team, you will work with industry leading semiconductor and system companies to deploy Cadence’s market leading Formal verification products. You will work with the North America based AE and sales teams to provide technical support in the Pre and Post-Sales process on Jasper Formal tool. You will be required to come up with innovative solutions to address our customer’s most challenging problems.


 Key responsibilities in this position are to:

  • Establish technical credibility and rapport with customers ranging from verification beginners to sophisticated experts.
  • Provide world-class reactive support, proactive training, and problem consultation to make our users successful.
  • Collaborate with R&D to introduce new simulation technologies.
  • Champion customer needs and help R&D and product engineers develop competitive and creative technical solutions.
  • Build verification environments (testbench creation)
  • Understand the competitive landscape and continuously work on differentiating Cadence’s solutions.

Minimum Requirements

  • BSE or graduation on related areas
  • Strong RTL understanding and coding
  • Knowledge of UNIX/Linux
  • Excellent English written and oral communication skills
  • Fluent in Portuguese: reading, writing and speaking
     

Nice to have skills

  • HDL languages such as VHDL, Verilog, SystemVerilog
  • Knowledge in Assertion (SVA, PSL)
  • Verification skills such as UVM testbench architecture, development and debug, assertion-based verification and formal verification testbenches
  • Scripting languages such as Perl, Python, TCL, C shell, Bash

Additional Job Details:

  • Employment category: CLT
  • Employment term: 40 hours/week
  • Location: R. Desembargador Jorge Fontana, 50, 7o andar, Belvedere - Belo Horizonte

Send email with resume to kemily@cadence.com, with the subject "SGV-TFO-Jasper-T1-Opportunity-R31581", and please include the following information: 1) Availability for interviews and contacts; 2) When can you start if you are selected; 3) Any salary and benefit requirements you consider important to mention. Deadline is March 31st, 2021.

About Cadence Design Systems:

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access [...] doing work that matters. Help us solve what others can’t.

Publicado 2 dias atrás desde Cadence Design Systems - View Original

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