Principal Asic Design Engineer

Techgig (Dublin, Ireland) 6 days ago

About Job

CTC Undisclosed Job Location Ireland Experience 10 - 13 yrs

Description

Dublin, Dublin

Company Description Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

As a member of Microchips engineering community, your primary responsibility will be to design, simulate, and verify the PCI Express supporting digital logic solutions for an advanced ASIC or FPGA. Microchips designs are an SOC with various Hard and Soft IP blocks that support a large number of industry standard protocols.

Duties & Responsibilities

General RTL and ASIC development
Detailed module design, performance analysis and detailed design specification creation
Participate in the RTL implementation, synthesis, formality check as well as ECOs
Support post-layout timing closure and verification
Participate in the investigation & assessment of emerging SerDes/Transceiver technologies & IPs
Improve Data & Command processing bandwidth, reduce latencies & increase reliability
Support porting the design into test chips and emulation platforms
Support pre-tapeout verification and post-tapeout validation/characterization of the system designed
Work closely with FPGA support software and FW engineers to resolve hardware issues and customer issues

PCI-Express Development

Integrate PCI Express logic into a final design, including resets, clock domain crossing, power-down controls, calibration logic, and associated register maps.
Work with 3rd party vendors for evaluation of potential IP cores and work with those IP providers to ensure robust, high bandwidth solutions.
Develop Block Level Constraints and run synthesis
Perform Static Timing Analysis of the PCI Express digital logic and review post-layout timing.
Support Verification and Validation groups in testing of the IP blocks and other similar logic blocks.
Integrate and simulate memory controller designs including

Integration into processor sub-systems as needed.
Integration into IP used in the FPGA fabric of the device.
Develop and/or integrate to industry standard Memory Controller Protocols

PCI-Express and related protocols such as CCIX and CXL
Other add-on protocols such as NVMe are a plus
Ongoing customer support to ensure the IP cores are robust with performance that meets the customer performance and/or power goals.
Support RTL design engineers with less experience for the functions shown above

Job Requirements

Experience is SOC IP development for PCI-Express and associated protocols
Strong Experience in RTL design, design verification, synthesis & formality
Strong Experience in Static Timing Analysis and Verilog simulation tools
Should be able to design complex state machines & data path logic
Ability to write detailed design specifications
Good analytical, oral, and written communication skills
Able to write clean, readable presentations.
Self-motivated, proactive team player.
Ability to work to schedule requirements.

Education Required

Bachelors/Masters in electrical engineering, Computer Engineering or Computer Science.

Experience Required

Minimum of 10 years of proven silicon design experience in high speed RTL design of PCI-Express, Ethernet and other related logic.

Beneficial Experience

FPGA and ASIC System On Chip Design Experience
Lab Experience for System Level Validation

Principal Asic Design Engineer

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