We have ownership AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, clock generation and distribution, etc.)
You will be working with multi-functional teams to define requirements/specs (e.g., modeling, package, board, DFT, ESD, etc.), crafting block-level specifications based on link-budget, behavioral modeling, and transistor-level feasibility. You will also drive mask design to implement layout view of designs. We also are working on Generation/QA of various IP Kit views/files for release to IP consumers, defining production/bench-level testplans, and conducting design reviews of blocks with peers/management to show design meets spec targets and requirements.