Engineer Stdcell Design

Micron (Hyderabad, AP, India) 1 day ago

Req. ID: 237341 

For nearly 40 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.  Our Global team is growing and we are looking for a passionate Memory Analog and Stdcell Characterization Validation Engineer in Micron Technology’s DRAM and Emerging Memory Group (DEG) in India.

As a Memory Analog and Standard cell Characterization Validation Engineer, you will work with a highly innovative and motivated design team using state of the art memory technologies to develop the most advanced DRAM and Emerging memory products. You will be challenged by the complexity and difficulty of verifying high density memory chips (up to 32Gb) with huge scale of circuit capability (over 10M transistors), ultra-high-speed designs, complex functionality which includes next Generation DDR/LPDDR (ex: DDR5, LPDDR5) and advanced low power and power management technologies. You will need to have the ability to work as a Memory Analog and Stdcell Characterization Validation Engineer, to verify and validate the Analog block circuitry and standard cells through the verification methodology and tools. You will work closely with Micron's various design and verification teams all over the world to contribute to the success of the design projects by applying verification tools and techniques, providing verification status and summaries to specific designs as needed


  • Design and Maintain standard cells for new products based on new technology.
  • Characterize the performance of standard cells and optimize the standard cell design and layout.
  • Characterization and modeling of Stdcell and specific Custom cells to provide timing/power model for verification.
  • Quality Analysis of characterized liberty models in terms of Timing, Power and Functionality.
  • Develop automation test bench/flow/tools to improve the work efficiency and help data analysis.
  • Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.
  • Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.


  • Good understanding of CMOS circuit design
  • Good knowledge of CMOS device physics and layout
  • Experience in SiliconSmart, Liberate, Liberate_LV, PT and Cadence Virtuoso preferred
  • Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, SimVision
  • Experience in Analog block design and verification preferred
  • Experience in Standard Cell design and verification preferred
  • Experience in using Skill, TCL, Perl, Python to do test bench automation and data analysis preferred
  • Previous work experience in DRAM memory related fields is a plus
  • Must possess good communication skills and ability to work well in a team


Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field with 2 years Industry relevant experience required


Hyderabad, Telangana

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s Human Resources Department at 1-800-336-8918 or 208-368-4748 and/or by completing our General Contact Form

Keywords:  Hyderabad || Andhra Pradesh (IN-AP) || India (IN) || DEG (DRAM Engineering Group) || Experienced || Regular || Engineering || #LI-SB1 || Tier 3 || 

Engineer Stdcell Design

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