Standard Cell Layout Engineer [Senior]

Micron (Hyderabad, AP, India) 1 hour ago

Req. ID: 236981 

About Micron

For more than 40 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

We are looking for standard layout engineer at our Micron Technology’s DEG Team in Hyderabad, India. As a Standard layout engineer, you will be working with an exceptionally talented, passionate core team based in India collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment.

Role and Responsibilities

  • Responsible for Design and development of standard cell layouts used in DRAM chips.
  • Perform layout verification like LVS/DRC/Latchup, quality check and documentation.
  • Responsible for on-time delivery of block-level layouts with satisfactory quality.
  • Demonstrate leadership Skills in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multi- project environment.
  • Guide junior team-members in their execution of Sub block-level layouts & review their work.
  • Contribute towards effective project-management.
  • Effectively communicate with engineering teams in the US, Japan and China and other global teams to assure the success of the layout project.


  • Must have 8 + years of experience in standard cell layout designs in advanced CMOS process.
  • Should have expertise in multiple standard cell layout library developments.
  • Should be able to perform standard cell layout development and physical verification activities for complex designs as per provided specifications.
  • Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.
  • Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
  • Should have adequate knowledge of schematics, interface with circuit designer and CAD team.
  • Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
  • Excellent in problem-solving skills in solving area, power, performance and physical verification of custom layout.
  • Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.
  • Should have leadership qualities and able to do multi-tasking as required.
  • Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.
  • Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.
  • Knowledge of Skill coding and layout automation is a plus.

BE/BTech or MTech in Electronic/VLSI Engineering or equivalent

 (we will also consider exceptionally talented Diploma holders in electronic or VLSI engineering)

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s Human Resources Department at 1-800-336-8918 or 208-368-4748 and/or by completing our General Contact Form

Keywords:  Hyderabad || Telangana (IN-TG) || India (IN) || DEG (DRAM Engineering Group) || Experienced || Regular || Engineering || #LI-SB1 || Tier 4 || 

Standard Cell Layout Engineer [Senior]

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