IO PADS and ESD Layout Engineer [Senior]

Micron (Hyderabad, AP, India) 1 day ago

Req. ID: 237001 

About Micron

For more than 40 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

We are looking for experience IO PADS and ESD layout design engineer for our Micron Technology’s DEG Team in Hyderabad, India. As an IO and ESD layout design engineer, you will be working with an exceptionally talented, passionate core team based in India collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment.

Job Location: Hyderabad, Telangana

Role and Responsibilities

  • Responsible for design and development of IO PADS/ESD Layouts and support full chip level integration.
  • Perform layout verification like LVS/DRC/Latchup, quality check and documentation.
  • Responsible for on-time delivery of block-level layouts with acceptable quality.
  • Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
  • Guide junior team-members in their execution of Sub block-level layouts & review their work
  • Contribute to effective project-management.
  • Effectively communicating with engineering teams in the US, Japan and China to assure the success of the layout project.

Qualification/Requirements

  • 8+ year experience in IO PADS/ESD layout design in advanced CMOS process.
  • Strong fundamentals in IO PADS, ESD concepts, wire bond and Flip chip layouts.
  • Familiar with different structures of IO Pad layouts and ESD structure.
  • Experience in failure mechanisms like antenna, latch-up, and ESD.
  • Exposure to Signal Integrity issues like EM and IR drop analyses.
  • Have worked on high-speed interfaces like DDR, Serdes, MIPI and understand the constraints of high-speed IO layout Design.
  • Understanding of layout effects on the circuit such as speed, capacitance, power and area etc.,
  • Ability to understand IO PAD design specifications and implement high-quality layouts.
  • Excellent command and problem-solving skills in physical verification of custom layout.
  • Excellent problem-solving skills in solving area, power, performance and physical verification of custom layout.
  • Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.
  • Should have leadership qualities and able to do multi-tasking as required.
  • Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.
  • Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.
  • Multiple Tape out support experience will be an added advantage.
  • Excellent verbal and written communication skills.

Education

BE or MTech in Electronic/VLSI Engineering

(we will also consider exceptionally talented Diploma holders in electronic or VLSI engineering)

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s Human Resources Department at 1-800-336-8918 or 208-368-4748 and/or by completing our General Contact Form


Keywords:  Hyderabad || Andhra Pradesh (IN-AP) || India (IN) || DEG (DRAM Engineering Group) || Experienced || Regular || Engineering || #LI-SB1 || Tier 4 || 

IO PADS and ESD Layout Engineer [Senior]

Apply On Company Site
Back to search page
;