A minimum with 10-14 years of total experience in full chip constraint development, Synthesis and STA
Strong Synthesis and STA fundamentals.
Must have proven experience constraint creation/development from scratch for full chip and SERDES/source synchronous designs including functional and DFT modes
Lead and developed constraints for designs with complex clocking schemes and scenarios
Experience in synthesis flow setup for full chip from scratch for optimal power, performance and area.
Experience in synthesis flows with UPF with multiple power islands
Experience handling STA of multi-power domain designs & constraint mode merging
STA flow development, abstraction with bottleneck identification
Generate timing ECOs for Physical design
Drive ambitious schedules, and enables dependent teams to accomplish
Has experience in mentoring junior engineers
Proficient in Tcl and Perl
Excellent analytical & communication skills
We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law. This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.
Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.
To request assistance with the application process, please contact Micron’s Human Resources Department at 1-800-336-8918 (or 208-368-4748).