Senior Engineer Digital Functional Verification (f/m/div*)

Infineon Technologies Austria AG (Villach, Österreich) Vor 15 Stunden veröffentlicht

Junior Digital Verification Engineer (f/m/div*) At a glance Do you want to be part of our success story? In this role you will work in an international team being responsible for...

Digital Design Engineer (f/m/div)* At a glance You are passionate about electronics? You are born into the world of semiconductors? To strengthen our team we are looking for a Digital...

At a glance

Do you want to become part of our Digital Verification Engineer Team? In this role you will work in an international team being responsible for the creation and improvements of verification environments and the execution on RTL and gate-level. If that sounds interesting to you, Apply now!

Quick info

Location

Entry level

3-5 years

Job ID

311467

Start

immediately

Type

Full time

Contract

Temporary

Job description

In your new job you will:

  • Create new and improve existing verification environments
  • Apply Universal Verification Methodology (UVM)
  • Define verification plans and setup verification metrics in digital and mixed-signal environments
  • Execute tests in these environments on RTL and gate-level
  • Closely cooperate with analog and digital designers as well as concept and verification engineers

Profile

You work conscientiously on making things better, faster, and more efficient and keep up high quality standards for yourself and other people. Your ability to quickly establish a successful cooperation helps you to gain trust within the team. Furthermore, you demonstrate strong communication skills and know how to establish lasting relationships and networks.

You are best equipped for this task if you have:

  • A degree in Electrical Engineering, Information Technology or Telematics with focus on electronics
  • Ideally 3-5 years of related work experience
  • Good knowledge of VHDL, Verilog, C
  • Good knowledge of Unix programming languages such as Shell, Perl, TCL etc
  • Experience at any level in Specman/e, SystemVerilog
  • Knowledge of SVAs, PSL, formal or mixed-signal verification as a plus
  • Functional verification experience as a plus
  • Fluent English skills with German skills as a plus

This position is limited to 10 month as maternity leave cover.
This position is subject to the collective agreement for workers and employees in the electrical and electronics industry, employment group G (https://www.feei.at/leistungen/informations-service/mindestlohne-und-gehalter-2020). A higher payment is negotiable depending on your expertise and skills. Furthermore, Infineon offers additional employee benefits.

About Us


Part of your life. Part of tomorrow.


We make life easier, safer and greener – with technology that achieves more, consumes less and is accessible to everyone. Microelectronics from Infineon is the key to a better future. Efficient use of energy, environmentally-friendly mobility and security in a connected world – we solve some of the most critical challenges that our society faces while taking a conscientious approach to the use of natural resources.

* The term gender in the sense of the General Equal Treatment Act (GETA) or other national legislation refers to the biological assignment to a gender group. At Infineon we are proud to embrace (gender) diversity, including female, male and diverse.

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