Sr. Engineer I-Validation

Microchip (Burnaby BC, Canada) 20 days ago

As a System Validation Engineer you will join group of talented professionals responsible for bring-up, integration and validation of System on a Chip (SoC) products for Scalable Storage Business Unit. This unit within the company is constantly involved with cutting-edge technology for data storage solutions and is one of the major developers of this technology on the world stage.





About the Job:

A validation engineer, in preparation for the “first silicon” arrival, is responsible for building infrastructure that is required to integrate and validate SOC for its intended use models. This involves building ecosystem, board designs, FW development, FPGA/CPLD coding, automation scripting, and software driver/OS system level integration.  In addition, in pre-prototyping phase, a validation engineer is involved in the functional emulation of the IC under development, involving VHDL/Verilog coding for internally designed or off the-shelf highly integrated FPGA platforms.





Upon prototype IC arrival (post-silicon), a validation engineer works in the lab environment and collaborates with design and FW engineers to bring-up, functionally integrate and validate entire SoC solution before it’s released to customers and mass production. Using the validation infrastructure together with the latest communication analyzers and test equipment, a validation engineer develops and executes a Feature Test Plan that fully exercises the prototype IC and associated FW/SW. The engineer utilizes existing and newly drafted standards including SAS, SATA, PCIe, NVMe, DDR, NAND Flash and other related standards commonly used in Storage Area Networks, Data Centers and Cloud.





Via this role a successful candidate will gain unique, in-depth knowledge at sub-block and system level of the storage product SoCs. A candidate will be involved in HW/FW integration, problem solving and validation process of multicore SoCs at pre and post silicon stages. The role opens wide growth opportunities and a gain of “jack of all trades” system engineering experience. 





Responsibilities

As a Scalable Storage BU System Validation Design Engineer, you will be involved in designing, building and debugging system level HW, FW and SW used to test leading edge prototype IC's in their intended applications. 





The responsibilities include but are not limited to:

•    As part of post-silicon system integration process, you will be involved in integration of a prototype IC FW/HW into a complete SoC solution.  This includes working with prototype boards, ICs, FW and SW to bring-up entire system level solution to life and enable its further FW development and testing.

•    You will work as part of a team to develop, execute and document a series of Feature Tests that will fully validate the operation of the SoC as part of the overall product. These feature tests will exercise the various functional blocks of an IC and associated FW/SW to ensure all components and overall SoC is functioning per design specs, achieves expected performance and meets industry standards.

•    Troubleshooting and resolving complex problems in embedded multi-core SoCs.

•    Developing FW for SoC test infrastructure and test cases.  

•    Building intended use model system solutions and utilizing them in End2End system level testing. 

•    Scripting for automated control of the test infrastructure.

•    Designing complex validation boards utilizing Microsemi and third-party IC's. 

•    FPGAs coding for device pre-proto emulation and testing.

•    Designing and VHDL coding of CPLDs and FGPAs residing on Validation boards.

•    Learning and dynamically applying knowledge of the SoC, protocols and standards. 

•    Effectively presenting technical information to small teams of engineers.



The role and responsibilities will grow with candidate skills and interests.


Sr. Engineer I-Validation

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