Typical Day in the Role
Purpose of the Team: The main function of Silicon Validation Engineer is to run, triage, and maintain silicon system regressions and report the results
Key projects:
Run and maintain silicon system regressions
Report results of silicon system regressions
Triage issues with various debugging tools
Review and validate any system updates made by other teams
Candidate Requirements
Disqualifiers:
Candidates unable to work onsite 5 days/week in Hillsboro lab environment
Candidates lacking hands-on engineering-level experience in silicon validation (technician-only profiles are not a fit)
No experience with PCIe, CXL, IO, endpoints (network/storage), or system-level validation
Must have their full 18months of tenure
Best vs. Average:
Bachelor's or master's degree in electrical engineering, computer engineering, or related field.
3+ years of experience in silicon validation, testing, or debugging.
Demonstrated validation experience in one or more of the following:
Validation of:
Functional: PCIe, CXL, IO, End Points (network, storage), Power Management, BIOS/FW development and debug.
Electrical: Serdes, IO
Applied understanding of Computer Architecture and CPU/SoC validation principles, including: Understanding of SoC subsystem, SoC system level, and platform level functionality and writing scripts/software with industry standard languages like Python or C/C++.
Understanding system level software and firmware.
Experience with hardware and software debug tools such as oscilloscopes, logic analyzers, JTAG, BERT, etc.
Proficient in scripting languages such as Python, C++.
Understanding of board level schematics.
Excellent problem-solving, analytical, and communication skills.
Skills:
Expertise in Python, C, and C++
Some knowledge of Verilog
Attention to detail; analytical and problem-solving ability
Explain a typical day in the role.:
Develop and execute validation test plans for various SoC features and subsystems in one of the following areas - functional, electrical, or power/performance.
Perform functional, stress, and performance testing using hardware and software tools.
Analyze test results and identify, isolate, and debug issues.
What is the ideal background of a candidate for this role?:
Engineering knowledge and experience with high-speed IO interfaces (PLL, PCI, CXL, etc.) and their interactions with other parts of the SoC, the platform, and software.
What are unique selling points that would get candidates interested in your role over another?:
Work on the state-of-the-art Compute SOC which powers Cloud infrastructure.
Top 3 Must-Have HARD Skills & years of experience for each:
Engineering level knowledge: PCIe, CXL, IO, End Points (network, storage), and debug. 3+ years
Electrical: Serdes, IO knowledge. 3+ years
Overall silicon validation knowledge. 3+ years
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