Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility Thoroughly comprehend both internal and external
Responsibilities: Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance Develop reusable testbench,
MinUSD $17.14/Hr. MaxUSD $26.56/Hr. Overview Registers, orders, labels specimens with appropriate barcode labels and receives all lab specimens arriving at MMC Lab for both inpatient, outpatient, and outreach services. Evaluates specimen received verses testing ordered and