Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in high-performance ASIC design. Experience architecting or designing RTL solutions for digital systems. Experience
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. Experience with
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Experience with scripting languages. Preferred qualifications: Masters degree or PhD in Electrical Engineering, Computer Engineering or Computer
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. Design experience
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: This individual independently plans, performs the moderately-defined responsibility for the digital architecture, design, Verilog RTL coding, implementation, and verification of next generation wireless and wired ASIC’s
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in ASIC design. Experience with SystemVerilog/RTL coding. Experience with scripting languages (e.g., Tcl, Python or
THE COMPANY Silvus Technologies, a leading provider of advanced MANET and MIMO communications systems, is reshaping mesh network technology for mission-critical applications – on the ground, in the air and at sea. Its battle-proven StreamCaster family
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in ASIC design, including one project focused on PCIe logic. Experience debugging RTL using
Minimum qualifications: Bachelors degree in Electrical Engineering or a related field, or equivalent practical experience. 8 years of experience with SystemVerilog, hardware design, automation, design verification test. 5 years of experience working with Computer-aided design (CAD).
Digital Design Engineer focusing on high-performance analog‑to‑digital and digital‑to‑analog converters. Responsibilities include RTL design, verification, behavioral modelling, and support of synthesis, timing closure, and P&R flow for the digital controller of high‑performance data converters in cutting‑edge technologies.
SpaceX is seeking a Design Verification Engineer (Silicon Engineering) to verify digital ASICs at block and system levels, develop testbenches, and drive pre‑ and post‑silicon validation. You will implement UVM or non‑UVM test environments, automate tests
About Us MicroVision is a global leader in innovative perception solutions, with offices in the U.S. and Germany. The company focuses on developing and supplying integrated lidar hardware and perception software to enhance safety and automation
A tech company in Cupertino is seeking an experienced ASIC/VLSI Design Engineer to design innovative communication systems. The role involves collaboration with multiple teams, RTL coding, and optimization of design for performance. Candidates should have over 5 years
We are seeking a Sr. RTL Verification Engineer to join our clients team in Redwood City who is inspired to bring the power of generative AI to enhance and speed the design and manufacture of complex semiconductors.
Omni Design Technologies, Inc. is seeking a Digital Design Engineer specializing in high-performance analog-to-digital and digital-to-analog converters. The role involves RTL design, verification, and modeling for cutting-edge data converter technologies. The ideal candidate will have a solid
Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional MTS Digital Design Engineering to join our Memory Interface Chip team in San Jose. In this
Job Details: Job Description: About Altera At Altera, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience. 2 years of experience in ASIC RTL design using systemverilog or verilog. Experience with industry-standard EDA tools for
Date Posted:2026-07-21 Country:United States of America Location:US-CA-GOLETA-B01 ~ 6825 Cortona Dr ~ BLDG B01 Position Role Type:Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements: U.S. citizenship is required, as only U.S. citizens are authorized to
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this