Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital design experience using SystemVerilog RTL. Experience with Computer Architecture. Preferred qualifications: Masters
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 2 years of experience with RTL Design. Experience with digital design, including synchronous and asynchronous logic, state machines,
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in high-performance ASIC design. Experience architecting or designing RTL solutions for digital systems. Experience
Minimum qualifications: Bachelors degree in Electrical Engineering or a related field, or equivalent practical experience. 8 years of experience with SystemVerilog, hardware design, automation, design verification test. 5 years of experience working with Computer-aided design (CAD).
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 1 year of experience in RTL design. Experience with digital design and microarchitecture design. Cross-functional experience with DV and
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Experience with scripting languages. Preferred qualifications: Masters degree or PhD in Electrical Engineering, Computer Engineering or Computer
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in ASIC design. Experience with SystemVerilog/RTL coding. Experience with scripting languages (e.g., Tcl, Python or
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience with digital design using SystemVerilog RTL. Experience with power, performance and area optimizations. Preferred qualifications:
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in ASIC design, including one project focused on PCIe logic. Experience debugging RTL using
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of Experience with RTL design (eg Verilog or System Verilog) and simulation (eg VCS or Incisive
Minimum qualifications: Bachelors degree in Electrical Engineering or a related field, or equivalent practical experience. 1 year of experience in software development, SystemVerilog, or electronic design automation (EDA). Experience with industry-standard tools, languages and methodologies relevant
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in RTL design. Experience with digital design and microarchitecture design. Cross-functional experience with DV and
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience with RTL coding using Verilog/SystemVerilog. Experience with industry-standard EDA tools for simulation, synthesis, and power
AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS’s services
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of industry experience with RTL design (e.g., Verilog or System Verilog) and simulation (e.g., VCS, Incisive
ASIC Digital Design, Sr Manager You are an experienced ASIC Digital Design Manager with strong hands-on expertise in USB digital design and architecture, capable of leading a team while remaining deeply engaged in technical execution. You