The application window is expected to close on: 09/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team Join the Cisco Silicon
The application window is expected to close on: 10/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team The Common Hardware Group
Posting number: 2026-FPS-014 Department: Dept. of Enterprise Services Division: Facility Professional Services Job classification: ENERGY/UTILITIES ENGINEER 3 Posting type: Open & Promotional Categories: Facility Management, Natural Resources, Project Management Summary Measurement and Verification (M&V) Specialist Energy/Utilities Engineer 3 Monday
Cupertino, California, United States Hardware Imagine what youll do at Apple! New insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and theres no
Amazon Annapurna Labs is seeking a Sr SOC Verification Engineer to verify custom SOC designs and mentor junior engineers. You will integrate IPs, develop testbenches, and drive rigorous coverage for quality silicon. Role requires 8+ years in SystemVerilog/UVM and
A leading technology company in Cupertino is seeking an experienced professional to join its Emulation verification team. The role involves working on verifying large SoCs and collaborating with various teams. Ideal candidates should have at least 10
Sr SOC Verification Engineer, Cloud-Scale Machine Learning Acceleration – Annapurna Labs Our Machine Learning Acceleration (MLA) team develops the Inferentia and Trainium SOCs that power today’s AI workloads in datacenters around the world. As a member of the
DescriptionOur Machine Learning Acceleration (MLA) team develops the Inferentia and Trainium SOCs that are used to power today’s AI workloads in datacenters all around the world. As a member of the Cloud-Scale Machine Learning Acceleration, you’ll
Parallel Wireless is reimagining mobile networks with innovative, energy-efficient Open RAN solutions. Join us as we lead the future of telecommunications, driving innovation through green and sustainable networks. Learn more about our mission, vision and values.
Have you ever wondered what it would be like to build massively scalable systems that are used by the worlds largest cloud infrastructures? Would you enjoy broad yet equally deep scope that impacts all AWS systems
Have you ever wondered what it would be like to build massively scalable systems that are used by the worlds largest cloud infrastructures? Would you enjoy broad yet equally deep scope that impacts all AWS systems
Company Overview Imagine a piloted air taxi that takes off vertically, then quietly carries you and your fellow passengers over the congested city streets below, enabling you to spend more time with the people and places
Company Overview Imagine a piloted air taxi that takes off vertically, then quietly carries you and your fellow passengers over the congested city streets below, enabling you to spend more time with the people and places
Position:Physical Design Engineer II (IC) Job Description: Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve
Position:Design For Test Engineer III (IC) Job Description: What Youll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern
The application window is expected to close on: 09/29/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This position requires that you live within
The application window is expected to close on: 08/31/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role is hybrid in San Jose,
Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are
The application window is expected to close on: 09/30/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This position requires that you live within
As a Sr ASIC validation engineer on our team, you will independently lead the SW driven early stages test development for our Trainium and Inferentia AI acceleration engines , drive the testing strategy at the sub system/