The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed to deliver high-quality clocking and reset logic to various units in
Our Team is building AI infrastructure and developer platform capabilities used by approximately 500 engineers. The team supports AI-native software development by improving shared tooling, platform workflows, and reusable technical building blocks across the engineering organization. As
Job Details: Job Description: About the Role Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team. In this role, you will own end-to-end verification of critical chassis and interconnect IP blocks from planning
Your work days are brighter here. We’re obsessed with making hard work pay off, for our people, our customers, and the world around us. As a Fortune 500 company and a leading AI platform for managing
Your work days are brighter here. We’re obsessed with making hard work pay off, for our people, our customers, and the world around us. As a Fortune 500 company and a leading AI platform for managing
Req ID: 131895 Region: Americas Country: USA State/Province: California City: San Jose Detailed Description - AI Architecture & Development: Lead the hands-on design and coding of RAG (Retrieval-Augmented Generation) architectures and agentic workflows. Build systems that allow
The future of software development is agentic. AWS is building Kiro — a frontier AI coding agent that tackles development tasks end-to-end, retains context across complex workflows, and continuously learns from its work. Kiro is already transforming
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 1 year of experience in RTL design. Experience with digital design and microarchitecture design. Cross-functional experience with DV
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in RTL design. Experience with digital design and microarchitecture design. Cross-functional experience with DV
Our Mission At Palo Alto Networks®, we’re united by a shared mission—to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking.
Production engineering is a field that involves crafting, building, and maintaining large-scale production systems with high efficiency and availability. It encompasses various areas, including software and systems engineering practices, storage, data management, and services. Professionals in
Req ID: 131895 Region: Americas Country: USA State/Province: California City: San Jose Detailed Description - AI Architecture & Development: Lead the hands-on design and coding of RAG (Retrieval-Augmented Generation) architectures and agentic workflows. Build systems that allow
DESCRIPTION Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group Software Engineering General Summary: Software Virtual Platform / Simulation; Sr. Engineer As a Software Virtual Platform Engineer, you will specialize in virtual platforms, including SystemC TLM and QEMU.
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group Software Engineering General Summary: This role is open to candidates based in these locations. Relocation will be required for candidates who are not currently located in Santa Clara,
Job Title: Principal Engineer, AI & ML Design Verification Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2517 Description: The Design Verification (DV) team
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group Software Engineering General Summary: This position is not eligible for Qualcomm immigration sponsorship. Open to Candidates in Santa Clara, Austin, San Diego, or Remote As a Software Virtual
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform