Job Details: Job Description: About Altera At Altera, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning
Minimum qualifications: Bachelors degree in Electrical Engineering, a related technical field, or equivalent practical experience. 1 year of experience in DFT architecture, implementation, Automatic Test Pattern Generation (ATPG), and verification for SoCs. Preferred qualifications: Masters degree in
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug)
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 3 years of experience in DFT architecture, implementation, Automatic Test Pattern Generation (ATPG), and verification for SoCs. Experience with
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in DFT architecture, implementation, and verification for SoCs. Experience in silicon bring-up, debug, or
The application window is expected to close on: 09/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team: The Common Hardware Group
The application window is expected to close on: 10/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team: The Common Hardware Group
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives communication and data processing transformation to
The application window is expected to close on: 09/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team: You will be part
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform
Position:Senior DFT Engineer (Einfochips) Job Description: What Youll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of gate-level synthesis and DFT stitch solutions for the Snapdragon chips powering billions of
SummaryAre you interested in working on tools and software that directly enable hardware validation? Our Hardware Test Engineering team is evolving our Design for Test (DFT) methodology, and were building the software infrastructure to support it effectively.
General Information Job Title DFT Architect, Product Engineering and Test Solutions-ATPG Job ID 17860 City Sunnyvale State/Province California Date Posted 08-Jun-2026 Job Category Engineering Job Subcategory Applications Engineering Hire Type Employee Remote Eligible No Base Salary Range:
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with DFT features (e.g., Joint Test Action Group (JTAG)/Memory Built-In Self-Test (MBIST)/Automatic Test Pattern
Scan insertion and ATPG tools (Synopsys, Cadence, Mentor). MBIST/OCC validation flows. Hierarchical DFT and SDC constraint management. Solid understanding of SSN design and JTAG standards for embedded instrumentation. Good understanding of SpyGlass DFT rules for design quality and
Director Of Design For Test (DFT) San Jose, California, United States Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential
About Mainspring Mainspring Energy manufactures and delivers fuel-flexible, low-emissions local power solutions that rapidly add new capacity and deliver reliable, affordable, and sustainable electric power. The company began commercial shipments of its Mainspring Linear Generators in
At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our