The application window is expected to close on: 10/02/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Who We Are: The Common Hardware Group
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 3 years of experience in DFT architecture, implementation, Automatic Test Pattern Generation (ATPG), and verification for SoCs. Experience with
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in DFT architecture, implementation, and verification for SoCs. Experience in silicon bring-up, debug, or
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of gate-level synthesis and DFT stitch solutions for the Snapdragon chips powering billions of
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug)
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About TylSemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of
Req ID: 140241 Region: Americas Country: USA State/Province: California City: San Jose Summary We are seeking a forward-thinking Technical Project Manager to spearhead transformative initiatives within our Test Engineering organization. In this cross-functional leadership role, you
Be part of Amazon LEO’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution
Be part of Amazon LEO’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution
DFT Design Engineering Director San Jose, California, United States Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with static timing analysis. Experience in Primetime or Tempus Tcl scripting and static
About Etched Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With
Voyager is an innovative defense, national security and space technology company committed to advancing and delivering transformative, mission-critical solutions. We tackle the most complex challenges to unlock new frontiers for human progress, fortify national security, and
Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and
Key Responsibilities: Design and implement sensor timing control logic and contribute to ISP system-level integration Participate in chip-level architecture definition, including analog interfaces, control logic, image data processing pipelines, and power/performance/area (PPA) trade-offs Integrate and validate
Company Description It started with a simple idea: what if surgery could be less invasive and recovery less painful? Nearly 30 years later, that question still fuels everything we do at Intuitive. As a global leader
Please Note: To conform with the United States Government Space Technology Export Regulations, the applicant must be a U.S. citizen, lawful permanent resident of the U.S., conditional resident, asylee or refugee (protected individuals as defined by
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in test engineering, product engineering or silicon quality/reliability. Experience in ASIC or SoC