About the Role: As the Hardware Lead, you will serve as the technical cornerstone driving the architecture and implementation of Reconceive’s next-generation analog MAC IP and custom memory. At Reconceive, we believe the future of AI
CMOS Layout Design Engineer – High-Speed Logic & Photonics A well-funded deep-tech semiconductor company is developing next-generation computing and connectivity technologies that combine advanced CMOS design with integrated photonics. The organization is building highly complex silicon platforms
Principal Substrate and Packaging Engineer Fully onsite in the San Francisco Bay Area Full time opportunity $400-500K total compensation package- base, bonus, stock (depends on skillset/experience level) Industry leader in semiconductor design focused on advanced IC packaging
Senior Technical Lead- TIA Design Full Time Opportunity Ideally on sight in the bay area (open to be flexible for the right candidate) 450K+ first year total compensation package (higher compensation packages depend on skillset/experience, open