Job Details: Job Description: About the Team Intel is seeking a motivated mid-level CAD/EDA Software Engineer to join the Silicon Chassis Automation Tool team. In this hands-on role, you will work closely with the tool lead
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group Systems Engineering General Summary: Qualcomm Data Center team is developing High performance, Energy efficient server solution for data center applications. We are looking for highly talented, innovative, teamwork-oriented
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: Qualcomm Data Center team is developing High performance, Energy efficient server solution for data center applications. We are looking for highly talented, innovative, teamwork-oriented
Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and
Senior Physical Design Engineer This role has been designed as Hybrid with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the
Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the
HCLTech is looking for a highly talented and self- motivated Silicon Interposer Design Engineer to join it in advancing the technological world through innovation and creativity. Job Title: Silicon Interposer Design Engineer Job REQ ID: 133407
Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that have been
Annapurna Labs (U.S.) Inc. is seeking a Sr. Package Layout Engineer in Cupertino, CA to lead the end-to-end physical design of advanced IC packages for ML and data center ASICs. The role requires 10+ years in
Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and
Role: SI/PI Engineer Location: Sunnyvale CA (Onsite only) Duration: 9+ Months Contract Job Description: Role Summary We are seeking an experienced SI/PI Engineer to join our Advanced Silicon Packaging team. In this role, you will be