Teradynes Memory Test Division in Tualatin, OR is seeking an experienced FPGA Engineering Manager to lead a small team and deliver advanced memory test solutions, combining digital and analog design with PCIe, DDR, and SERDES interfaces.
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradynes test technology ensures your device works right the first time, every time! Our portfolio of
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradynes test technology ensures your device works right the first time, every time! Our portfolio of
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradynes test technology ensures your device works right the first time, every time! Our portfolio of
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradynes test technology ensures your device works right the first time, every time! Our portfolio of
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradynes test technology ensures your device works right the first time, every time! Our portfolio of
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradynes test technology ensures your device works right the first time, every time! Our portfolio of
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Location: Tualatin, OR; San Jose, CA, US Opportunity Overview Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting‑edge memory test solutions. MTD
Teradynes Memory Test Division (MTD) in Tualatin, OR seeks a hands-on FPGA Engineering Manager to lead a small team delivering memory test solutions. The role combines technical oversight, project management, and direct engineering contributions to ensure
FPGA Engineering Manager (Memory Test, Tualatin, OR) Date: Jul 13, 2026 Location: Tualatin, OR, US Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Manager to support the development of our growing portfolio
Select how often (in days) to receive an alert: FPGA Engineering Manager (MTD, Tualatin, OR) Date: Jul 13, 2026 Location: Tualatin, OR, US We are the global test and automation specialists, powering next-generation technologies through sophisticated