Apple Inc. in Cupertino, CA is seeking an SOC/ASIC Integration & Synthesis Engineer to drive front-end integration activities including RTL integration, synthesis, UPF and ECO, while advancing low-power methodologies and power verification at the chip level. You
Job Details: Job Description: About Altera At Altera, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading
The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality for mixed signal SOC. The candidate should have
Job Description Renesas Electronics is seeking a highly skilled and motivated Staff Digital Design Engineer to join our growing hardware development team in Chandler, AZ. In this role, you will be responsible for designing power and
Description Are you mechanically inclined, or enjoy hands on hobbies and want to learn a new skill? Then United Plastic Fabricating is your next career move! UPF, a family-owned company since 1986 and innovators of plastic products
Job Details: Job Description: About Altera At Altera, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading
Job Details: Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience. 2 years of experience in ASIC RTL design using systemverilog or verilog. Experience with industry-standard EDA tools
AIML enhanced Design/Verification Methodology Engineer This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing
The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across
Job Details: Job Description: The Role and Impact As a DFT Design Engineer, you will play a pivotal role in shaping Intels silicon solutions. Your contributions will directly influence the quality and efficiency of Intels products,
Job Details: Job Description: Intels HIPD team is looking for an experienced senior Logic design engineer to join the rapidly growing UCIE PHY IP for Intels flagship datacenter/server designs. Responsibilities will include but not limited to:
Requisition ID: 295441 Relocation Authorized: National - Family Telework Type: Full-Time Office/Project Work Location: Oak Ridge, TN Extraordinary teams building inspiring projects: Since 1898, we have helped customers complete more than 25,000 projects in 160 countries
Senior Design Verification Engineer This role has been designed as Hybrid with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience verifying digital logic at RTL using SystemVerilog for ASICs or FPGAs. Experience verifying digital
Job Details: Job Description: Job Description Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of
Job Details: Job Description: The Role and Impact As a Senior CPU Physical Design Engineer, you will play a critical role in delivering Intels next-generation high-performance CPUs from concept through manufacturing. You will drive physical implementation
Description Shift: Wednesday, Thursday, Friday, Saturday 10 hour days Requirements Willing to be a hands-on leader with strong communication and computer skills Strong analytical skills. Ability and desire to build strong relationships and collaborate well with
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in implementation of CPU cache subsystems, including load-store unit or private/shared L2/L3 designs. Experience
Our Solution Engineering division is seeking a skilled verification engineer to develop testbenches and test suites to join our diverse team. Arm’s hardware is at the heart of the computing and connectivity revolution that continues to