Grow with us Principal RTL Methodology Architect, Austin, Texas On-Site, Hybrid work schedule. This is not a remote work opportunity. ASIC / SoC Architecture | RTL Design Methodology | IP Reuse Platforms | RTL Quality Signoff About Us: The
Schweitzer Engineering Laboratories, Inc. (SEL) designs, manufactures, and installs world-class products and solutions for use in critical infrastructure, making electric power safer, more reliable, and more economical. SEL is hiring a Hardware Engineer with a focus
SummarySpecify, design and help in the verification and lab bring up of advanced mixed-signal circuits (digital side). DescriptionIn this job, you will be responsible for RTL coding of blocks specified by you or others for advanced mixed signal
SummaryAt Apple, we work every day to craft products that enrich peoples lives. If youre passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is
SummaryAt Apple, we work every day to craft products that enrich people’s lives. If you’re passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 10 years of experience with IP Development or Integration. Experience in ASIC development with Verilog or VHDL (Vhsic
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in high-performance ASIC design. Experience architecting or designing RTL solutions for digital systems. Experience
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. Experience with
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: This individual independently plans, performs the moderately-defined responsibility for the digital architecture, design, Verilog RTL coding, implementation, and verification of next generation wireless and wired ASIC’s
Job Details: Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs. Participates actively
Job Title: Microarchitect & RTL Design Engineer Location: Santa Clara, CA About the Role: We are seeking a seasoned Microarchitect and RTL Design Engineers with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key
The Opportunity: We are seeking a highly-skilled Senior Software Engineer to join a team of passionate engineers that are tasked with the unique opportunity to build next-generation platforms that will pave the path for many other
Modern Health Modern Health is a mental health benefits platform for employers. We are the first global mental health solution to offer employees access to one-on-one, group, and self-serve digital resources for their emotional, professional, social,
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: This individual leads, plans, synthesizes ambiguous or conflicting requirements and performs the complex responsibility of performing block level verification for complex, multi-feature designs using
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture
Responsibilities MaxLinear is seeking a Senior Principal Digital Design Engineer to join our team. In this role, you will focus on the following: Define microarchitecture for complex subsystems (e.g., 200/400G 802.3, PCIe 6/7, DSP, FEC, data
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have
About ARSIEM Corporation At ARSIEM Corporation we are committed to fostering a proven and trusted partnership with our government clients. We provide support to multiple agencies across the United States Government. ARSIEM has an experienced workforce
Position Title: Senior FPGA Engineer Requisition ID: 1806 Position Location: Fairfax, VA Position Reports To: Senior Manager, FPGA Engineering Supervises Others: No At Trident Systems Space Electronic Systems (SES) division, we believe in the power of