Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in high-performance ASIC design. Experience architecting or designing RTL solutions for digital systems. Experience
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. Experience with
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Experience with scripting languages. Preferred qualifications: Masters degree or PhD in Electrical Engineering, Computer Engineering or Computer
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. Design experience
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: This individual independently plans, performs the moderately-defined responsibility for the digital architecture, design, Verilog RTL coding, implementation, and verification of next generation wireless and wired ASIC’s
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in ASIC design. Experience with SystemVerilog/RTL coding. Experience with scripting languages (e.g., Tcl, Python or
THE COMPANY Silvus Technologies, a leading provider of advanced MANET and MIMO communications systems, is reshaping mesh network technology for mission-critical applications – on the ground, in the air and at sea. Its battle-proven StreamCaster family
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in ASIC design, including one project focused on PCIe logic. Experience debugging RTL using
Minimum qualifications: Bachelors degree in Electrical Engineering or a related field, or equivalent practical experience. 8 years of experience with SystemVerilog, hardware design, automation, design verification test. 5 years of experience working with Computer-aided design (CAD).
THE COMPANY Silvus Technologies, a leading provider of advanced MANET and MIMO communications systems, is reshaping mesh network technology for mission-critical applications – on the ground, in the air and at sea. Its battle-proven StreamCaster family
Pay Rate: $80.00/hr to $86.00/hr Position: ASIC/RTL Design Engineer Location: San Jose, CA - Onsite Duration: 06 months Contract (possibility of extension) Job Description: The work will expose the designer to a number of IP including ARM
This is a Senior/Staff-level ASIC/RTL Design Engineer role requiring 10+ years of industry experience in end-to-end SoC design. The strongest candidates should have hands-on expertise in RTL coding, micro-architecture, ASIC design flow, verification/debug, synthesis, timing closure, and silicon bring-up,
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience. 2 years of experience in ASIC RTL design using systemverilog or verilog. Experience with industry-standard EDA tools for
Date Posted:2026-07-21 Country:United States of America Location:US-CA-GOLETA-B01 ~ 6825 Cortona Dr ~ BLDG B01 Position Role Type:Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements: U.S. citizenship is required, as only U.S. citizens are authorized to
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this
Job Details: Job Description: Intels HIPD team is looking for an experienced senior Logic design engineer to join the rapidly growing UCIE PHY IP for Intels flagship datacenter/server designs. Responsibilities will include but not limited to:
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group Video Systems, HW Architecture General Summary: Qualcomm’s Computer Vision Systems team is building the intelligence behind the world’s most advanced Snapdragon‑powered devices, from next‑generation mobile phones to autonomous
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience architecting RTL solutions employing software based construction, instantiation, customization or generation of RTL. Experience with industry-standard
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In Create Account) 2. If you already have a Candidate Account, please
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience in RTL design. Experience with digital design and microarchitecture design. Experience in design optimizing for