Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in high-performance ASIC design. Experience architecting or designing RTL solutions for digital systems. Experience
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. Experience with
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Experience with scripting languages. Preferred qualifications: Masters degree or PhD in Electrical Engineering, Computer Engineering or Computer
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. Design experience
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in ASIC design. Experience with SystemVerilog/RTL coding. Experience with scripting languages (e.g., Tcl, Python or
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in ASIC design, including one project focused on PCIe logic. Experience debugging RTL using
Minimum qualifications: Bachelors degree in Electrical Engineering or a related field, or equivalent practical experience. 8 years of experience with SystemVerilog, hardware design, automation, design verification test. 5 years of experience working with Computer-aided design (CAD).
Company:Qualcomm Atheros, Inc. Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: This individual independently plans, performs the moderately-defined responsibility for the digital architecture, design, Verilog RTL coding, implementation, and verification of next generation wireless and wired ASIC’s
Pay Rate: $80.00/hr to $86.00/hr Position: ASIC/RTL Design Engineer Location: San Jose, CA - Onsite Duration: 06 months Contract (possibility of extension) Job Description: The work will expose the designer to a number of IP including ARM
This is a Senior/Staff-level ASIC/RTL Design Engineer role requiring 10+ years of industry experience in end-to-end SoC design. The strongest candidates should have hands-on expertise in RTL coding, micro-architecture, ASIC design flow, verification/debug, synthesis, timing closure, and silicon bring-up,
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience. 2 years of experience in ASIC RTL design using systemverilog or verilog. Experience with industry-standard EDA tools for
Job Details: Job Description: Intels HIPD team is looking for an experienced senior Logic design engineer to join the rapidly growing UCIE PHY IP for Intels flagship datacenter/server designs. Responsibilities will include but not limited to:
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience architecting RTL solutions employing software based construction, instantiation, customization or generation of RTL. Experience with industry-standard
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Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience in RTL design. Experience with digital design and microarchitecture design. Experience in design optimizing for
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group Modem Technologies General Summary: Qualcomm is the world’s largest fabless semiconductor company and a global leader in wireless innovation—powering the majority of 3G, 4G, and 5G devices while
Meta is seeking highly skilled Design Engineers to join our team. In this role, you will contribute to the development of advanced technology solutions, including machine learning and network acceleration. You will collaborate with researchers and
Sr. ASIC Design Engineer This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in RTL design. Experience with digital design and microarchitecture design. Experience in optimizing for performance,