Circuit Methodology Engineering Manager NVIDIA is seeking a Circuit Methodology Engineering Manager to lead a team responsible for EDA tool evaluation, workflow integration, and strategic vendor engagement for the mixed signal circuit design organization. This manager will
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with
Company Description Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful
Job Details: Job Description: About Altera At Altera, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading
General Information Job Title Staff Technical Product Manager – Electronics AI & HPC Simulation Job ID 18158 City Sunnyvale State/Province California Date Posted 08-Jul-2026 Job Category Product Management Job Subcategory Technical Product Management Hire Type Employee
About the Job The preferred location of this role is Bay Area (CA) We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of
AIML enhanced Design/Verification Methodology Engineer This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing
Position:Physical Design Engineer II (IC) Job Description: Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers
Senior Design Verification Engineer This role has been designed as Hybrid with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the
Senior Design Verification Engineer This role has been designed as Hybrid with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the
Position:Design For Test Engineer III (IC) Job Description: What Youll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern
The application window is expected to close on: 09/30/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This position requires that you live within
General Information Job Title UCIe Applications Engineering Architect Job ID 16991 City Sunnyvale State/Province California Date Posted 14-Apr-2026 Job Category Engineering Job Subcategory Applications Engineering Hire Type Employee Remote Eligible No Base Salary Range: $184000 -
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,
Job Details: Job Description: About Intel: At Intel, we strive to create innovative technologies that shape the future of computing and empower every person and organization on the planet. This position offers a unique opportunity to
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in physical design, including custom structured datapath implementation. Experience hardening dense compute units
Position Overview: Support and enhance the Analog CAD design flow across the full custom IC design cycle, including schematic, layout, simulation, and physical verification using Cadence Virtuoso and Calibre tools. Responsibilities: Support and optimize Analog CAD flows
Company:Qualcomm Atheros, Inc. Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Qualcomm-Atheros, a.k.a. QCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group Systems Engineering General Summary: Qualcomm Data Center team is developing High performance, Energy efficient server solution for data center applications. We are looking for highly talented, innovative, teamwork-oriented
Company:Qualcomm Atheros, Inc. Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Qualcomm-Atheros, a.k.a. QCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and