Amazons Annapurna Labs seeks a Sr. Physical Design Verification Engineer to lead full chip verification efforts and collaborate with layout teams in Cupertino/Austin. You will drive methodologies, tape-out readiness, and mentorship, shaping cloud silicon excellence. The role requires deep
Annapurna Labs (U.S.) Inc. is seeking an ASIC Physical Design Integration and Verification Engineer to join the backend team. You will ensure the quality and manufacturability of complex semiconductor designs through physical verification and floorplan sign-off for AWS data-center silicon,
Description Annapurna Labs (our organization within AWS Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom
Sr. Physical Design Verification Engineer, Annapurna Labs Annapurna Labs (our organization within AWS Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time
Amazons Annapurna Labs in Cupertino seeks a Physical Design Verification Manager to lead the verification strategy for complex SoCs, including ownership and automation of the verification process. The ideal candidate has a strong background in EE/CS, over 10 years of
Physical Design Verification Manager, Annapurna Labs Annapurna Labs (our organization within AWS Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—
Description Annapurna Labs (our organization within AWS Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom
Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and
Job Details: Job Description: About Altera At Altera, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading
AIML enhanced Design/Verification Methodology Engineer This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the
Design Verification Manager This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this
Position:Physical Design Engineer II (IC) Job Description: Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to
Senior Design Verification Engineer This role has been designed as Hybrid with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global
Senior Design Verification Engineer This role has been designed as Hybrid with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global
SummaryAt Apple we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity
The application window is expected to close on: 09/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team Join the Cisco Silicon
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in physical design, including custom structured datapath implementation. Experience hardening dense compute units (such
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: As a Physical Design Clock Engineer, you will work with microarchitecture, RTL design, CAD, block level and top level physical design teams to create best in
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives digital transformation to help create a