Position:Sr DFT Engineer (eInfochips Inc) Job Description: What Youll Be Doing: Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level Verify test patterns using gate-level simulations. Collaborate closely with Synthesis, STA
Job Details: Job Description: About Altera: Accelerating Innovators — Altera provides leadership programmable solutions that are easy to use and deploy, across the cloud to the edge, enabling limitless possibilities for AI. Our broad portfolio includes
Job Details: Job Description: About Altera At Altera, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning
Minimum qualifications: Bachelors degree in Electrical Engineering, a related technical field, or equivalent practical experience. 1 year of experience in DFT architecture, implementation, Automatic Test Pattern Generation (ATPG), and verification for SoCs. Preferred qualifications: Masters degree in
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug)
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 3 years of experience in DFT architecture, implementation, Automatic Test Pattern Generation (ATPG), and verification for SoCs. Experience with
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in DFT architecture, implementation, and verification for SoCs. Experience in silicon bring-up, debug, or
The application window is expected to close on: 09/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team: The Common Hardware Group
The application window is expected to close on: 10/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team: The Common Hardware Group
Scan insertion and ATPG tools (Synopsys, Cadence, Mentor). MBIST/OCC validation flows. Hierarchical DFT and SDC constraint management. Solid understanding of SSN design and JTAG standards for embedded instrumentation. Good understanding of SpyGlass DFT rules for design quality and
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakthrough data transport and acceleration
We are looking for a creative and experienced ATE Test Engineer. NVIDIA has continuously reinvented itself over three decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern
At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our
Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform
Responsibilities: Develop, debug, and release ATE test programs on Teradyne J750 and UltraFLEXplus using IG-XL Own tester setup, configuration, and correlation from bench to ATE Support facility and tester infrastructure bring-up (power, cooling, networking, safety, handler/prober
The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed to deliver high-quality clocking and reset logic to various units in
Our Mission At Palo Alto Networks®, we’re united by a shared mission—to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking.