Minimum qualifications: Bachelors degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience. 4 years of experience with custom silicon design (e.g., SoCs, ASICs, etc.). Experience with RTL design using Verilog
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in ASIC design. Experience with SystemVerilog/RTL coding. Experience with scripting languages (e.g., Tcl, Python
About the Team OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is building next-generation AI-native silicon and infrastructure to support large-scale training and inference systems.
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience with digital design using SystemVerilog RTL. Experience with power, performance and area optimizations. Preferred qualifications:
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: We are seeking a highly skilled and versatile engineer who thrives at the intersection of RTL design and CAD automation. This role is ideal for
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: This individual leads the team to improve engineering efficiency, product quality and responsibility of the improving engineering efficiency, product quality and responsibility for CPU
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in ASIC design, including one project focused on PCIe logic. Experience debugging RTL using
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: We are hiring talented engineers for RISCV CPU RTL development targeting high-performance, low-power devices. In this role, you will contribute to architecture and product definition
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: We are hiring talented engineers for RISCV CPU RTL development targeting high-performance, low-power devices. In this role, you will contribute to architecture and product definition
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. In this role, you will work with chip architects
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. Design experience
SummarySpecify, design and help in the verification and lab bring up of advanced mixed-signal circuits (digital side). DescriptionIn this job, you will be responsible for RTL coding of blocks specified by you or others for advanced mixed
SummaryAt Apple, we work every day to craft products that enrich peoples lives. If youre passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group CPU Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform
General Information Job Title Applications Engineering, Sr Staff Engineer- RTL-to-GDS/Fusion Compiler Job ID 13802 City Sunnyvale State/Province California Date Posted 15-Dec-2025 Job Category Engineering Job Subcategory Applications Engineering Hire Type Employee Remote Eligible No Base Salary Range:
FPGA/RTL Design Engineer to design, implement, and validate digital circuits and FPGA-based solutions. This role involves hands-on development using RTL languages, FPGA design tools, and simulation environments, while also supporting customers and creating technical assets that enable successful
Hiring: RTL Design Engineer Location: Bay Area, USA Employment Type: Full-Time We are looking for an experienced RTL Design Engineer to join a leading semiconductor team working on next-generation ASIC/SoC designs. Key Responsibilities: Design, develop, and debug synthesizable
Our client is looking FPGA / RTL Design Engineer for Long term project in San Jose, CA (Onsite) Below is the detail requirement. Job Title: FPGA / RTL Design Enginee rLocation: San Jose, C A Job Descriptio n:FPGA/RTL Design
JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and AMD internal IPs. Successful candidates will be responsible for leading, and participating in, the