Principal Substrate and Packaging Engineer Fully onsite in the San Francisco Bay Area Full time opportunity $400-500K total compensation package- base, bonus, stock (depends on skillset/experience level) Industry leader in semiconductor design focused on advanced IC packaging and high‑speed
CMOS Layout Design Engineer – High-Speed Logic & Photonics A well-funded deep-tech semiconductor company is developing next-generation computing and connectivity technologies that combine advanced CMOS design with integrated photonics. The organization is building highly complex silicon
R&D Technical Project Manager Vector Network Analyzer Product Technologies (MMICs, SiPs, Subsystems) Keysight drives innovation in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees build world-class solutions across communications, 5G/6G, automotive, energy, quantum,