At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design Engineering Intern The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry
Company Description Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful
Job Details: Job Description: About Altera At Altera, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradynes test technology ensures your device works right the first time, every time! Our portfolio of
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience. 2 years of experience in ASIC RTL design using systemverilog or verilog. Experience with industry-standard EDA tools
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in high-performance ASIC design. Experience architecting or designing RTL solutions for digital systems.
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development.
AIML enhanced Design/Verification Methodology Engineer This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing
Position:Physical Design Engineer II (IC) Job Description: Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers
Senior Design Verification Engineer This role has been designed as Hybrid with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the
Senior Design Verification Engineer This role has been designed as Hybrid with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the
Position:Design For Test Engineer III (IC) Job Description: What Youll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG
Company Description At Intuitive, we are united behind our mission: we believe that minimally invasive care is life-enhancing care. Through ingenuity and intelligent technology, we expand the potential of physicians to heal without constraints. As a
The application window is expected to close on: 09/30/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team The Common Hardware Group
The application window is expected to close on: 08/31/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role is hybrid in San Jose,
SummaryAt Apple we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity
The application window is expected to close on: 09/30/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This position requires that you live within
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from
As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of Hardware in our data centers including technologies such as AWS Inferentia which is a machine learning inference
Meta is hiring ASIC EDA Infrastructure Engineers within our Infrastructure ASIC organization. We are looking for individuals with experience in EDA flow and methodology, CAD/automation and ASIC infrastructure to build System on Chip (SoC) and IP