Minimum qualifications: Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field or equivalent practical experience. 5 years of experience in performance modeling, computer architecture, or hardware/software co-design. Experience with programming in C++ or
Brief Description Commercial Training Design + Delivery Manager Overview The Commercial Training Design + Delivery Manager will lead the design, development, and delivery of commercial training programs that elevate the performance of Pulmonx’s customer-facing teams. This is a hands-on content and capability
Req ID: 138675 Region: Americas Country: USA State/Province: California City: San Jose Summary We are seeking a high-impact, visionary Senior Principal AI Engineer to architect, design, and oversee the next generation of our enterprise hardware intelligence platform.
Staff Engineer, Design Engineering Req ID: 137022 Region: Americas Country: USA State/Province: California City: San Jose Summary The Signal Integrity Engineer will play a critical role in the planning of digital PCB designs, simulation, lab verification, and troubleshooting
Req ID: 137901 Region: Americas Country: USA State/Province: California City: San Jose Summary The role is for a highly accomplished and forward-thinking Senior Director, Technical Engineer for a leading role in a critical customer engagement. This
Job Details: Job Description: About Altera At Altera, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading
Zoox is on a mission to reimagine transportation and ground-up build autonomous robotaxis that are safe, reliable, clean, and enjoyable for everyone. We are still in the early stages of deploying our robotaxis on public roads,
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience. 2 years of experience in ASIC RTL design using systemverilog or verilog. Experience with industry-standard EDA tools for
Minimum qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience. 2 years of experience working in a hardware design technical environment, or 1 year of experience with an advanced degree.
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in high-performance ASIC design. Experience architecting or designing RTL solutions for digital systems. Experience
Minimum qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience. 4 years of experience working in product safety, or 3 years of experience with an advanced degree. Preferred qualifications:
Minimum qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. Experience
AIML enhanced Design/Verification Methodology Engineer This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the
Design Verification Manager This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people
Company OverviewKLA is a global leader in diversified electronics for the semiconductor manufacturing ecosystem. Virtually every electronic device in the world is produced using our technologies. No laptop, smartphone, wearable device, voice-controlled gadget, flexible screen, VR
Job Details: Job Description: Intels HIPD team is looking for an experienced senior Logic design engineer to join the rapidly growing UCIE PHY IP for Intels flagship datacenter/server designs. Responsibilities will include but not limited to: - Develops
As a global leader in cybersecurity, CrowdStrike protects the people, processes and technologies that drive modern organizations. Since 2011, our mission hasn’t changed — we’re here to stop breaches, and we’ve redefined modern security with the
Senior Design Verification Engineer This role has been designed as Hybrid with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global
Senior Design Verification Engineer This role has been designed as Hybrid with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global
The application window is expected to close on: 08/21/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role requires the employee to work